Finishing Touches in Routing

•         If you have thin tracks (<25 thou) then it’s nice to add a “chamfer” to any “T” junctions, thus eliminating any 90 degree angles. This makes the track more physically robust, and prevents any potential manufacturing etching problems. But most importantly, it looks nice.
• Check that you have any required mounting holes on the board. Keep mounting holes well clear of any components or tracks. Allow room for any washers and screws.

• Minimise the number of hole sizes. Extra hole sizes cost you money, as the manufacturer will charge you based on not only the number of holes in your boards, but the number of different hole sizes you have. It takes time for the very high speed drill to spin down, change drill bits, and then spin up again. Check with your manufacturer for these costs, but you can’t go wrong by minimising the number of hole sizes.

• Double check for correct hole sizes on all your components. Nothing is more annoying than getting your perfectly laid out board back from the manufacturer, only to find that a component won’t fit in the holes! This is a very common problem, don’t get caught out.

• Ensure that all your vias are identical, with the same pad and hole sizes. Remember your pad to hole ratio. Errors here can cause “breakouts” in your via pad, where the hole, if shifted slightly can be outside of your pad. With plated through holes this is not always fatal, but without a complete annular ring around your hole, your via will be mechanically unreliable.

• Check that there is adequate physical distance between all your components. Watch out for components with exposed metal that can make electrical contact with other components, or exposed tracks and pads.

• Change your display to “draft” mode, which will display all your tracks and pads as outlines. This will allow you to see your board “warts and all”, and will show up any tracks that are tacked on or not ending on pad centers.

• If you wish, add “teardrops” to all your pads and vias. A teardrop is a nice “smoothing out” of the junction between the track and the pad, not surprisingly, shaped like a teardrop. This gives a more robust and reliable track to pad interface, better than the almost right angle between a standard track and pad. Don’t add teardrops manually though, it’s a waste of time. But if your program supports automatic teardrop placement, feel free to use it.

Basic Routing

Routing is also known as “tracking”. Routing is the process of laying down tracks to connect components on your board. An electrical connection between two or more pads is known as a “net”.

• Keep nets as short as possible. The longer your total track length, the greater it’s resistance, capacitance and inductance. All of which can be undesirable factors.

• Tracks should only have angles of 45 degrees. Avoid the use of right angles, and under no circumstances use an angle greater than 90 degrees. This is important to give a professional and neat appearance to your board. PCB packages will have a mode to enforce 45 degree movements, make use of it. There should never be a need to turn it off. Contrary to popular belief, sharp right angle corners on tracks don’t produce measurable EMI or other problems. The reasons to avoid right angles are much simpler - it just doesn’t look good, and it may have some manufacturing implications.

• Forget nice rounded track corners, they are harder and slower to place and have no real advantage.Stick to 45 degree increments. Rounded track bends belong to the pre-CAD taped artwork era. 

• “Snake” your tracks around the board, don’t just go “point to point”. Point to point tracking may look more efficient to a beginner at first, but there are a few reasons you shouldn’t use it. The first is that it’s ugly, always an important factor in PCB design! The second is that it is not very space efficient when you want to run more tracks on other layers.

• Enable your Electrical grid, which is sometimes referred to as a “snap to center” or “snap to nearest” option. Let the software find the centers of pads and ends of tracks automatically for you. This is great for when you have pads and tracks which aren’t lined up to your current snap grid. If you don’t have these options enabled then you may have to keep reducing your snap grid until you find one that fits. Far more trouble than it’s worth. There is almost never a reason to have these options disabled.

• Always take your track to the center of the pad, don’t make your track and pad “just touch”. There are few reasons for this. The first is that it’s sloppy and unprofessional. The second is that your program may not think that the track is making electrical connection to the pad. Proper use of a snap grid and electrical grid will avoid problems here.

• Use a single track, not multiple tracks tacked together end to end. It may make no difference to the look of your final board, but it can be a pain for future editing. Often you’ll have to extend a track a bit. In this case it’s best to delete the old one and place a new one. It may take a few extra seconds, but it’s worth it. People looking at your finished board may not know, but YOU’LL know! It’s the little touches like this that set good PCB designers apart.

• Make sure your tracks go right through the exact center of pads and components, and not off to one side. Use of the correct snap grid will ensure that you get this right every time. If your track doesn’t go through the exact center then you are using the wrong snap grid. Why do you need to do this? It makes your board neater and more symmetrical, and it gives you the most clearance.

• Only take one track between 100 thou pads unless absolutely necessary. Only on large and very dense designs should you consider two tracks between pads. Three tracks between pads is not unheard of, but we are talking seriously fine tolerances here.

• For high currents, use multiple vias when going between layers. This will reduce your track impedance and improve the reliability. This is a general rule whenever you need to decrease the impedance of your track or power plane.

• Don’t “drag” tracks to angles other than 45 degrees

•  “Neck down” between pads where possible. Eg, a 10 thou track through two 60 thou pads gives a generous 15 thou clearance between track and pad.

• If your power and ground tracks are deemed to be critical, then lay them down first. Also, make your power tracks as BIG as possible.

•  Keep power and ground tracks running in close proximity to each other if possible, don’t send them in opposite directions around the board. This lowers the loop inductance of your power system, and allows for effective bypassing.

• Keep things symmetrical. Symmetry in tracking and component placement is really nice from a professional aesthetics point of view.

• Don’t leave any unconnected copper fills (also called “dead copper”), ground them or take them out.

• If you are laying out a non-plated through double sided board, then there are some additional things to watch out for. Non-plate through holes require you to solder a link through the board on both the top and bottom layer.

• Do not place vias under components. Once the component is soldered in place you won’t be able to access the joint to solder a feed through. The solder joint for the feed through can also interfere with the component.

• Try and use through hole component legs to connect top tracks to bottom tracks. This minimizes the number of vias. Remember that each via adds two solder joints to your board. 

• The more solder joints you have, the less reliable your board becomes. Not to mention that that it takes a lot longer to assemble.

PCB Layout measurement

GRID	.020 or 8.333 for thru-hole parts .005, .010 or .025 for surface mount
PIN 1 ON COMPONENTS	.055 SQ. (Comp & Solder Side)
COMPONENT PADS	.055 RD. min. of .020 larger than hole size
COMPONENT HOLES	.033 +/-.003, .039 +/-.003 for .025 sq. pins (e.g. Headers, Connectors)
SOLDERMASK PADS	.065 (.010 larger for wet mask, .005 for dry or L.P.I.
PADS PLANE CLEARANCE	.085 min or .030 larger than hole size. Do not use a pad within a clearance. Remove unused pads on internal line layers. The potential for shorts will be greatly reduced.
THRU-HOLE VIA PADS	.050 Rd.
THRU-HOLE VIA HOLE	.028 +/- .003 separate tool number for easy removal for later test fixture use.
SMT VIA PADS	.028 min., .042 preferred
SMT VIA HOLES	.012 min., .022 preferred
BOARD EDGE PULL BACK ON PLANES	.050
BOARD EDGE PULL BACK ON SOLDERMASK	.025 keep circuitry .050 from board edge.
SIGNAL TRACE	.008 (.012 on loose boards)
PWR & GND TRACES	.050
LINE TO LINE SPACING	.007 (.013 on loose boards)
LINE TO PAD SPACING	.007 on SMT, .008 on thru-hole
PAD TO PAD SPACING	.025 Pad to via and pad to pad spacing should be sufficient to insure soldermask coating between pads. Soldermasks are bigger, so allow enough room between pads for a minimum of .015 coverage.
PAD TO VIA CENTERS	.080
TEXT HEIGHT	.075 min.
TEXT LINE WIDTH	.008 min.
PART OUTLINE WIDTH	.012 min.

Ground Bounce

As digital devices become faster, their output switching times decrease.
Faster switching times cause higher transient currents in outputs as they
discharge load capacitances. These higher currents, which are generated
when multiple outputs of a device switch simultaneously from a logic
high to a logic low, can cause a board-level phenomenon known as
ground bounce.

Many factors contribute to ground bounce. Therefore, no standard test
method predicts ground bounce magnitude for all possible PCB
environments. Determine each condition’s and each device’s relative
contributions to ground bounce by testing the device under these
conditions. Load capacitance, socket inductance, and the number of
switching outputs are the predominant conditions that influence the
magnitude of ground bounce in programmable logic devices.


Design Recommendations
Altera recommends the following design methods to reduce ground
bounce:
■ Add the recommended decoupling capacitors for as many
VCC/GND pairs as possible.
■ Place the decoupling capacitors as close as possible to the power and
ground pins of the device.
■ Add external buffers at the output of a counter to minimize the
loading on Altera device pins.
■ Configure the unused I/O pin as an output pin and then drive the
output low. This configuration acts as a virtual ground. Connect this
low driving output pin to GNDINT and/or the board’s ground plane.
■ For MAX 7000AE devices, any unused I/O pin may be driven to
ground by programming the “programmable ground” bit (one per
I/O cell). In doing so, the macrocell will not need to be sacrificed, but
can still be used as a buried macrocell.
■ When speed is not critical, turn on the slow slew rate logic option for
APEXTM II, APEXTM 20K, MercuryTM, ExcaliburTM, FLEX® 10K,
FLEX 8000, FLEX 6000, MAX 9000, MAX 7000A, and MAX 7000
designs.
■ Limit load capacitance by buffering loads with an external device,
such as the 74244 IC bus driver, or by reducing the number of devices
that drive the bus.
■ Eliminate sockets whenever possible.
■ Reduce the number of outputs that can switch simultaneously
and/or distribute them evenly throughout the device.
■ Move switching outputs close to a package ground pin.
■ Create a programmable ground next to switching pins.
■ Eliminate pull-up resistors or use pull-down resistors.
■ Use multi-layer PCBs that provide separate VCC and ground planes.
■ Add 10- to 30-Ω resistors in series to each of the switching outputs to
limit the current flow into each of the outputs.
■ Create synchronous designs that will not be affected by momentarily
switching pins.
■ Assign I/O pins to minimize local bunching of output pins.

■ Place the power and ground pins next to each other. The total
inductance will be reduced by mutual inductance, since current flows
in opposite directions in power and ground pins.
■ Use a bigger via size to connect the capacitor pad to the power and
ground plane to minimize the inductance in decoupling capacitors.
■ Use the wide and short trace between the via and the capacitor pad
or place the via adjacent to the capacitor pad.

■ Use surface mount capacitors to minimize the lead inductance.
■ Use low effective series resistance (ESR) capacitors. The ESR should
be < 400 mΩ.
■ Each GND pin/via should be connected to the ground plane
individually.
■ To add extra capacitance on the board, Altera recommends placing a
ground plane next to each power (VCC) plane. This placement gives
zero lead inductance and no ESR. The dielectric thickness between
the two planes should be ~5 mils.

Routing Practices

Signal Routing
Microstrip or stripline routing are ways to route signals on a PCB.
Microstrip routing refers to a trace routed on an outside layer of the PCB
separated by a dielectric from the reference plane (GND or VCC). Stripline
routing refers to a trace routed on an inside layer with two reference
planes.


Clock Signal Routing

Considering routing techniques can help to maximize the quality of clock
transmission lines. Use the following routing techniques for clock signals:
■ Avoid using serpentine routing; clock traces should be as straight as
possible.
■ Avoid using multiple signal layers for clock signals.
■ Avoid using vias in the clock transmission line, since vias can
contribute impedance change and reflection.
■ Route the clock trace on the microstrip (preferably top layer) to
minimize the use of vias and delays, since air is the dielectric material.
Air has the lowest dielectric constant (Er = 1).
■ Place a ground plane next to the outer layer to minimize noise. If
using the inner layer for routing the clock trace, sandwich the layer
by ground planes to reduce delay.
■ Terminate clock signals properly.


Differential Signal Routing

For quality signal transmission, consider routing techniques of
differential signals in PCB designs. Use the following techniques for
differential signal routing:
■ Make D > 2S to minimize crosstalk. See Figure 5.
■ Route the two traces of a differential pair as close to each other as
possible after they leave the device to ensure minimal reflection.
■ Maintain a constant distance between the two traces of a differential
pair over their entire length.
■ Keep the electrical length between the two traces of a differential pair
the same. This minimizes the skew and phase difference.
■ To minimize impedance mismatch and inductance, avoid using vias.

Power Supply De-coupling

Power supply de-coupling is now standard practice in digital design but we’ll mention it here because of its importance in removing supply line noise.
High-frequency noise on power supplies causes problems for nearly every digital device. Such noise is typically generated by ground bounce, radiating signals or even by the digital device itself.
The simplest method of curing power supply noise is to use de-couple the high-frequency noise to ground via capacitors. Ideally, the de-coupling capacitors provide a low-impedance path to ground for the high-frequency noise, hence ‘cleaning’ the power supply.
The choice of de-coupling capacitors depends on the application. Most designs will locate surface mount chip capacitors as close to the power pins as physically possible. The value of these capacitors must be great enough to provide a low-impedance path for the anticipated power supply noise.


A common problem with de-coupling capacitors is that they often don’t behave like capacitors. There are several reasons for this :
• The capacitor packaging includes some amount of lead inductance;
• Capacitors also have an amount of Equivalent Series Resistance (ESR);
• The trace between the power pin and the de-coupling capacitor has some amount of series inductance;
• The trace between the ground pin and the ground plane also has some amount of series inductance.


The cumulative effect of these problems is that:
1. The capacitor will resonate at a particular frequency and the impedance of the network will greatly change as that frequency is neared;
2. The ESR hampers the low-impedance path for the high-speed noise being de-coupled.



There are several things a digital designer can to counter these effects:
1. The traces emanating from the Vcc and GND pins on the device need to be as low-inductance as possible. This is done by making them as short and wide as the physical constraints allow.
2. Choosing a capacitor with a lower ESR will improve the power supply de-coupling.
3. Choosing a smaller package for the capacitor will reduce the package inductance. The trade-off for using a smaller package is the capacitance variation over temperature. After selecting a capacitor, these specs need to be verified for the design requirements.


The last point can introduce a trap for the unwary. For example, using a Y5V capacitor instead of an X7R device may allow for a smaller package and hence lower inductance, but this is at the cost of poor performance at high temperature.
A further point to consider is that a larger capacitor is often employed to provide bulk storage on the board as well as implementing low-frequency de-coupling. These capacitors are distributed more sparingly and are often electrolytic or tantalum devices.

Crosstalk

Crosstalk is yet another major concern for PCB designers. The cross section of a PCB indicating three parallel traces and their associated electromagnetic (EM) fields. When the spacing between the traces is too narrow, the EM fields of the traces will interact and the signals on the traces become corrupted . This is called crosstalk.

Crosstalk can be corrected by increasing the spacing between the spacing between tracks. However, PCB designers are under constant pressure to shrink their layouts and hence reduce the gap between tracks. Also, there are times when a designer has no alternative but to wear some amount of crosstalk in their design. Clearly, PCB designers need a strategy of managing crosstalk.
Many ‘rules of thumb’ have been published over the years about what is an acceptable spacing between conductors. A common rule is the 3W rule where the spacing between traces must be at least three times the width of the trace.
However the reality is that ‘acceptable’ spacing between conductors depends upon the application, the environment and the design margins. The spacing between traces changes from one situation to another and must be calculated for each. Furthermore, there are times when crosstalk can’t be avoided and the impact of crosstalk must be calculated. In these situations there is no substitution for a computer simulation.
A good example of these issues is in high-speed, high-density connectors. Here the PCB designer may know that there is some amount of crosstalk between the conductors and he/she can’t do anything about it because the geometry of the connector is fixed. By using a simulator, the designer can determine the impact on the signal integrity and can evaluate the effects on the system.

Signal Routing

An important part of ensuring signal integrity is in the physical routing of signal traces. The PCB designer is often under pressure, not only to shrink designs but also to maintain signal integrity. Finding the balance is a matter of knowing where problems can occur and how far the envelope can be pushed before the system fails.
High-speed currents cannot cope with discontinuities in the signal trace. Among the most common and problematic discontinuity is the right-angled corner . Whilst right-angled corners work without problem at low-frequencies, at high-speeds they radiate. Instead, right-angles can be replaced by a mitred 90º corner, or by two spaced 45º corners.
Corners tighter than 90º should not even be considered for high-speed signals.



Another common problem is stub traces. Unless there is a specific reason for using them, all stubs should be eliminated from the board. The problem is that at high frequencies, stubs can radiate as well as creating a host of impedance problems for signal traces.
Yet another key area in high-speed design is the routing of differential pairs. Differential pairs operate by driving two signal traces in a complementary fashion. Differential pairs offer excellent immunity to noise and improved S/N ratio. However there are two constraints in realising these advantages:
1. The two traces must be routed adjacent to each other; and
2. The two traces must be matched in length

Printed Circuit Board (PCB) for Surface Mounting (SMT)

Printed Circuit Board (PCB) for Surface Mount Technology (SMT)need to be choosen wisely taking into consideration factors such as CTE (Coefficient of Thermal Expansion), cost, dielectric properties and Tg.

When designing surface mounting board (PCB), the selection of substrate is basically determined by the type of SMD components to be used. In any Electronics manufacturing or PCB assembly, when leadless ceramic chip carriers (LCCC) are mounted on printed circuit boards made out of glass epoxy substrates, solder joints cracking is generally seen about 100 cycles. The cause of the excessive stress is the CTE differential between the ceramic package and the glass epoxy substrate. 

There are three different approaches to solder joint cracking problems: 

Using a substrate with a compatible CTE;

Using a compliant top layer substrate; and

Replacing leadless ceramic packages with leaded ones.

The most widely used substrate for SMT Printed Circuit Boards, is glass epoxy. It entails no CTE compatibility problems when used for plastic surface mount packages. However, This provides the solution for commercial applications only.  

The most commonly used substrate for pcbs for military applications is one with a CTE value compatible with that of the ceramic packages that has been specified. Each PCB substrate option has its own advantages and disadvantages. Designers need to be carefully balances the constraints of cost with reliability and performance needs. In addition, solder masks and via hole sizes should be selected carefully.

Most Important EMC Design Guidelines

Minimize the loop areas associated with high-frequency power and signal currents.

This simple rule is on nearly everybody's list of EMC guidelines, but it often gets ignored or compromised in favor of other guidelines. Often the board designer doesn't even know where the signal currents flow. Digital circuit designers like to think of signals in terms of their voltage. Signal integrity and EMC engineers must think of signals in terms of their current.

There are two things that every good circuit designer should know about signal currents.

1. Signal currents always return to their source (i.e. current paths are always loops)

2. Signal currents take the path(s) of least impedance.

At megahertz frequencies and higher, signal current paths are relatively easy to identify. This is because the path of least impedance at high frequencies is generally the path of least inductance, which is generally the path that minimizes the loop area. Currents return as close as possible to the path of the outgoing current. At low frequencies (generally kHz frequencies and below), the path of least impedance tends to be the path(s) of least resistance. Low frequency currents are more difficult to trace, since they will spread out. Significant current return paths may be relatively distant from the outgoing current path.

Don't Split, Gap or Cut the Signal Return Plane

Sure, there are some situations where a well-placed gap in the return plane is called for. However, these are relatively rare and always involve a need to control the flow of low-frequency currents. The safest rule-of-thumb is to provide one solid plane for returning all signal currents. In situations where you expect that a particular low-frequency signal is susceptible or is capable of interfering with the circuitry on your board, use a trace on a separate layer to return that current to its source. In general, never split, gap or cut your board's signal return plane. If you are convinced that a gap is necessary to prevent a low-frequency coupling problem, seek advice from an expert. Don't rely on design guidelines or application notes and don't try to implement a scheme that "worked" in someone else's "similar" design.

Don't Locate High-Speed Circuitry between Connectors

Among board designs that we have reviewed or evaluated in our lab, this is one of the most common problems we've encountered. Many times simple board designs that should have had no trouble at all meeting EMC requirements at no additional cost or effort, wind up being heavily shielded and filtered because they violated this simple rule.

Why is the location of connectors so important? At frequencies below a few hundred megahertz, wavelengths are on the order of a meter or longer. Any possible antennas on the printed circuit board itself tend to be electrically small and therefore inefficient. However, cables or other devices connected to a board can serve as relatively efficient antennas.

Signal currents flowing on traces and returning through solid planes result in small voltage differences between any two points on the plane. These voltage differences are generally proportional to the current flowing in the plane. When all connectors are placed along one edge of a board, the voltage between them tends to be negligible. However, high-speed circuitry located between connectors can easily develop potential differences of a few millivolts or greater between the connectors. These voltages can drive currents onto attached cables causing a product to exceed radiated emissions requirements.

Control Signal Transition Times

A board operating with a clock speed of 100 MHz should never fail to meet a radiated emissions requirement at 2 GHz. A well-formed digital signal will have a significant amount of power in the lower harmonic frequencies, but not so much power in the upper harmonics. Power in the upper harmonic frequencies is best controlled by controlling the transition times in digital signals. Longer transition times are preferred for EMC. Excessively long transition times can cause signal integrity and thermal problems. An engineering compromise must be reached between these competing requirements. A transition time that is approximately 20% of a bit period results in a reasonably good-looking waveform, while minimizing problems due to crosstalk and radiated emissions. Depending on the application, transitions times may need to be more or less than 20% of the bit period, however transitions times should not be left to chance.

There are three common methods for controlling rise and fall times in digital logic.

1. Use a logic family that is only as fast as the application requires.

2. Put a resistor or a ferrite in series with a device's output.

3. Put a capacitor in parallel with a device's output.

The first choice is often the easiest and most effective option. However, the use of a resistor or ferrite gives the designer more control and is less affected by changes that occur in logic families over time. Capacitors can actually increase the amount of high-frequency current drawn by the source device and in most cases are not an appropriate choice.

Note that it is never a good idea to try to slow down or filter a single-ended signal by impeding the flow of current in the return path. For example, one should never intentionally route a low-speed trace over a gap in a return plane in an attempt to filter out the high-frequency noise. After reviewing the first two design guidelines, this should be obvious. Nevertheless, boards employing this flawed design strategy occasionally show up in our lab.

http://www.cvel.clemson.edu/emc/tutorials/guidelines/Important_Guidelines.html

Impedance Definitions

 Differential Impedance Definitions
♦ Single-Ended Impedance (Zo)
Impedance on a single line with respect to
ground when not coupled to another line (Zo = Square root of Zodd Zeven)
♦ Differential Impedance (ZDIF)
The impedance on one line with respect to the coupled line, when the
lines are driven by equal and opposite signals
♦ Odd Mode Impedance (ZOdd)
Impedance on a single line with respect to ground when the other
coupled line is driven by equal and opposite signals (ZDIF = 2ZOdd)
♦ Common Mode Impedance (ZCM)
Impedance of the two lines combined with respect to ground
♦ Even Mode Impedance (ZEven)
The impedance on one line with respect to ground when the coupled
line is driven by an equal and in-phase signal (ZEven = 2ZCM)

PWB Materials and Considerations

PWB Materials
♦ Dozens of dielectric materials to chose from
- Rogers 20 types
- Taconic 10 types
- Polyclad 25 types
- Park Nelco 30 types
♦ Several dielectric thickness options
♦ Several copper thickness options
♦ Two copper plating options
- Rolled
- Electro-Deposited


Electrical Considerations in
Selecting Materials
♦ Dielectric Constant (permittivity)
- The more stable, the better
- Lower values may be more suitable for high layer counts
- Higher values may be more suitable for some RF structures
♦ Loss Tangent
- The lower, the better
- Becomes more of an issue at higher frequencies
♦ Moisture Absorption
- The lower, the better
- Can effect dielectric constant and loss tangent
♦ Voltage Breakdown
- The higher, the better
- Typically not an issue, except in high voltage applications
♦ Resistivity
- The higher, the better
- Typically not an issue, except in low leakage applications


Mechanical Considerations in
Selecting Materials
♦ Peel Strength
- The higher, the better
♦ Flammability
- UL Standards
♦ Glass Transition Temperature (Tg)
♦ Thermal Conductivity
- Typically PWB material is considered an insulator
- Thermal Clad (Bergquist)
- Planes & vias contribute to thermal conductivity
♦ Coefficient of Expansion
- XY matching to components, solder joint stress (LCC)
- Z axis expansion, via stress
♦ Weight (density)
♦ Flexibility



Dielectric, Common Thickness Dielectric, Common Thickness
♦ Core Material
- 0.002, 0.003, 0.004, 0.005, 0.006, 0.007, 0.008, 0.009
- 0.010, 0.012, 0.014, 0.015, 0.018, 0.020, 0.031
♦ Pre-Preg
- 0.002, 0.003, 0.004, 0.005, 0.008
- Pre-preg can be stacked for thicker layers
♦ Use standard thickness in designing stack-up
♦ Work with anticipated PWB vendor(s) when
assigning stack-up and selecting material