Ground Bounce

As digital devices become faster, their output switching times decrease.
Faster switching times cause higher transient currents in outputs as they
discharge load capacitances. These higher currents, which are generated
when multiple outputs of a device switch simultaneously from a logic
high to a logic low, can cause a board-level phenomenon known as
ground bounce.

Many factors contribute to ground bounce. Therefore, no standard test
method predicts ground bounce magnitude for all possible PCB
environments. Determine each condition’s and each device’s relative
contributions to ground bounce by testing the device under these
conditions. Load capacitance, socket inductance, and the number of
switching outputs are the predominant conditions that influence the
magnitude of ground bounce in programmable logic devices.


Design Recommendations
Altera recommends the following design methods to reduce ground
bounce:
■ Add the recommended decoupling capacitors for as many
VCC/GND pairs as possible.
■ Place the decoupling capacitors as close as possible to the power and
ground pins of the device.
■ Add external buffers at the output of a counter to minimize the
loading on Altera device pins.
■ Configure the unused I/O pin as an output pin and then drive the
output low. This configuration acts as a virtual ground. Connect this
low driving output pin to GNDINT and/or the board’s ground plane.
■ For MAX 7000AE devices, any unused I/O pin may be driven to
ground by programming the “programmable ground” bit (one per
I/O cell). In doing so, the macrocell will not need to be sacrificed, but
can still be used as a buried macrocell.
■ When speed is not critical, turn on the slow slew rate logic option for
APEXTM II, APEXTM 20K, MercuryTM, ExcaliburTM, FLEX® 10K,
FLEX 8000, FLEX 6000, MAX 9000, MAX 7000A, and MAX 7000
designs.
■ Limit load capacitance by buffering loads with an external device,
such as the 74244 IC bus driver, or by reducing the number of devices
that drive the bus.
■ Eliminate sockets whenever possible.
■ Reduce the number of outputs that can switch simultaneously
and/or distribute them evenly throughout the device.
■ Move switching outputs close to a package ground pin.
■ Create a programmable ground next to switching pins.
■ Eliminate pull-up resistors or use pull-down resistors.
■ Use multi-layer PCBs that provide separate VCC and ground planes.
■ Add 10- to 30-Ω resistors in series to each of the switching outputs to
limit the current flow into each of the outputs.
■ Create synchronous designs that will not be affected by momentarily
switching pins.
■ Assign I/O pins to minimize local bunching of output pins.

■ Place the power and ground pins next to each other. The total
inductance will be reduced by mutual inductance, since current flows
in opposite directions in power and ground pins.
■ Use a bigger via size to connect the capacitor pad to the power and
ground plane to minimize the inductance in decoupling capacitors.
■ Use the wide and short trace between the via and the capacitor pad
or place the via adjacent to the capacitor pad.

■ Use surface mount capacitors to minimize the lead inductance.
■ Use low effective series resistance (ESR) capacitors. The ESR should
be < 400 mΩ.
■ Each GND pin/via should be connected to the ground plane
individually.
■ To add extra capacitance on the board, Altera recommends placing a
ground plane next to each power (VCC) plane. This placement gives
zero lead inductance and no ESR. The dielectric thickness between
the two planes should be ~5 mils.